The field of the invention is that of high speed CMOS logic, in particular that of lookahead adders.
In the field of high speed dynamic CMOS circuits, there have been several efforts to reduce the delay of high fan-in circuits by using the dynamic differential circuit and sense-amplifier (sense-amp) together. Recent circuit styles use differential cascode voltage logic (DCVS) for the logic evaluation tree.
FIG. 1A shows in simplified form, a prior art circuit diagram, including sense amp 1 and logic evaluation circuit 15xe2x80x2. The CLK signals are applied to equilibrate the Q and Q# nodes (using the convention that Q# means the logic complement of Q) of the sense amp to VDD and the delayed CLK signal opens a current path to ground. Clocked footer transistors 16 and 16xe2x80x2 provide the optional ability to cut off current flow te ground and cause the transistors in units 15 and 15xe2x80x2 to float up to some voltage above ground.
Logic tree circuit 15xe2x80x2 performs the logic analysis and applies a differential input to nodes Q and Q#. Sense amp 1 will respond to the differential signal once the difference exceeds the noise level and will drive nodes Q and Q# to the rails.
The invention relates to a multi-bit high speed adder employing a two level lookahead carry structure.
A feature of the invention is a 64-bit adder implemented in partially depleted silicon on insulator technology and having only two levels of lookahead carry implemented in sense-amp based differential logic.
Another feature of the invention is the use of a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier.
Yet another feature of the invention is the use of partially depleted silicon on insulator technology in the evaluation tree, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.